1. Field of the Invention
The present invention relates to a clock interruption detection circuit, and particularly to a clock interruption detection circuit suitable for fabrication in a semiconductor integrated circuit.
2. Description of the Prior Art
A clock interruption detection circuit receives an external clock and, upon detecting an absence of the clock, operates to fix the operation of a logic circuit operating in synchronism with the clock, in order to prevent an abnormal operation of the logic circuit.
In the prior art, such clock interruption detection circuit is generally constructed in several ways. One is where two systems of external clock signals are input and the interruption of either clock signal is detected. Another is based an the use of a free-running oscillator (i.e., there are two clock systems) in order to detect clock interruption. Still another example employs an analog integrating circuit (which is mounted externally to the semiconductor IC) whose outputs are compared in two comparators to detect clock interruption.
However, there is a growing need to use a single system of clock signal and to fabricate the clock interruption circuit in an LSI.
To respond to such needs, Japanese Unexamined Patent Publication No. H5-153102 proposes a stable clock interruption detection circuit as shown in FIG. 8. This clock interruption detection circuit is based on a combination of a delay circuit and logic circuits whereby the size of the apparatus can be minimized by integration, the adjustment of the elements is unnecessary and there is no deterioration with time.
Referring to FIG. 8, the clock interruption detection circuit according to the above-mentioned disclosure comprises a delay circuit 102 for delaying a clock 101, an exclusive OR circuit 104 for exclusively ORing the clock and an output 103 of the delay circuit 102, and a three-state buffer 108. The three-state buffer 108 has its output control terminal connected to the output of the exclusive OR circuit 104. When the output of the exclusive OR circuit 104 is at a high level, the output of the three-slate buffer 108 is enabled. When the output of the OR circuit is at a low level, the output of the three-state buffer 108 assumes a high-impedance state. In the event of a clock signal loss, the voltage at the output terminal of the three-state buffer 108 decreases in the high-impedance state, thereby allowing the clock interruption to be detected.
However, in this clock interruption detection circuit shown in FIG. 8, with regard to the relationship between the delay time in the delay circuit 102 and the clock interruption detection time (a reference duration of time for the determination of clock interruption in the absence of the clock signal), the detection time must by designed by the leak current of the three-state buffer 108. Accordingly, the clock interruption detection time varies depending on the value of the leak current of the three-state buffer 108. It is also necessary to provide a capacitor at the output terminal 109 so as to fix the output level.
In view of the foregoing problems of the prior art, it is an object of the present invention to provide a clock interruption detection circuit which can detect clock interruption by using a single system of input clock, which is suitable for integration and which can set the clock interruption detection time with precision.
The object of the invention is achieved by a clock interruption detection circuit according to the present invention comprising:
a circuit for generating a first and a second signal, the first signal formed by a pulse signal synchronized with a leading edge of a frequency divided clock which is obtained by frequency-dividing an input clock in a frequency divider with a predetermined division value, the second signal being formed by a pulse signal synchronized with a trailing edge of the frequency divided clock;
a first and a second switch with a control terminal supplied with the first and the second signal, respectively, the first and said second switches controlling the on/off of a discharge path of a first and a second capacitor which are charged by a power supply, wherein the first and the second capacitors are charged by the power supply when the first and the second switched are turned off, respectively;
a first and a second waveform-shaping buffer circuit which are supplied with a terminal voltage of the first and the second capacitor, respectively; and
a circuit for selectively outputting one of outputs of the first and the second waveform-shaping buffer circuit.
The first and second capacitors may preferably be charged when the first and second switches are turned off by the power supply via a first and a second resistor. The time constant of terminal voltage increase during the charging of the capacitors is determined by the resistance values of the resistors and the capacitance of the capacitors.
In another aspect of the present invention, the clock interruption detection circuit comprises:
a frequency division circuit for outputting a plurality of frequency divided clocks by dividing an input clock with different division values;
a first AND circuit for ANDing the input clock and the plurality of frequency divided clocks;
an inverter for inverting one of the frequency divided clocks with the largest division value,
a second AND circuit for ANDing the input clock, the frequency divided clock(s) other than the frequency divided clock with the largest division value and the output of the inverter;
a first switch with a control terminal supplied with the output of the first AND circuit for controlling the on/off of a discharge path of a first capacitor;
a second switch with a control terminal supplied with the output of the second AND circuit for controlling the on/off of a discharge path of a second capacitor;
a first waveform-shaping buffer circuit supplied with a terminal voltage of the first capacitor;
a second waveform-shaping buffer circuit supplied with a terminal voltage of the second capacitor; and
a selection circuit supplied with the outputs of the first and second waveform-shaping buffer circuits for selectively outputting one of these outputs based on a selection control signal obtained by delaying the output of the inverter by a predetermined length of time in the frequency divided clock signal with the largest division value (or the output of the inverter) by a predetermined length of time in the delay circuit.
In a yet another aspect of the present invention, the clock interruption detection circuit comprises:
a frequency divider circuit supplied with an input clock for generating a frequency divided clock with a predetermined division value;
a first AND circuit for ANDing the input clock and the frequency divided clock;
an inverter for inverting the frequency divided clock;
a second AND circuit for ANDing the input clock and the output of the inverter;
a first and a second switch with a control terminal supplied with the outputs of the first and second AND circuits for controlling the on/off of a discharge path of a first and a second capacitor;
a first and a second waveform-shaping buffer circuit supplied with a terminal voltage of the first and the second capacitor; and
a selection circuit supplied with the outputs of the first and second waveform-shaping buffer circuits for selecting and outputting one of those outputs in accordance with a selection control signal obtained by delaying the output of the inverter for a predetermined length of time by the delay circuit.
As a first advantageous effect of the present invention, the interruption of the clock can be detected without providing an oscillator other than the input clock.
This is because of the fact that the present invention comprises two CR circuits so that when a clock interruption occurs, either one of the capacitors is always charged, which allows the clock interruption to be detected without providing the oscillator other than the input clock.
A second advantageous effect of the present invention is that an increase in the chip area can be minimized when the clock interruption detection circuit is fabricated in an LSI.
This is because of the use of the Schmitt trigger buffers instead of analog circuitry such as comparators in the present invention for the detection of the output voltage level.
A third advantageous effect of the present invention is that the time for detecting the clock interruption can be precisely set even when the clock interruption detection circuit is fabricated in an LSI and when the capacitors or resistance values are varied within the CR circuits. This is because in the present invention, the outputs of the CR circuits are switched by the selector at intervals of a plurality of periods of the input clock, which makes it possible to set the time constant of the CR circuits above the plurality of clock periods.